A 1.2-V feedforward amplifier and a/d converter for mixed analog/digital lsis

IEICE Transactions on Electronics

Volumn E79-C, Issue 12, 1996, Pages 1666-1677

  Matsuura, Tatsuji ^a   Imaizumi, Eiki ^a   Anbotî, Takanobu ^a  

^a HITACHI LTD   (Japan)

Author keywords

Analog; Feedforward amplifier; Low power; Low voltage; Pipeline a d convener

Indexed keywords

ANALOG TO DIGITAL CONVERSION; CURRENT VOLTAGE CHARACTERISTICS; DIGITAL CIRCUITS; ENERGY DISSIPATION; ENERGY UTILIZATION; INTEGRATED CIRCUIT LAYOUT; LINEAR INTEGRATED CIRCUITS; LOGIC GATES; NUMERICAL METHODS; OPERATIONAL AMPLIFIERS; POWER CONVERTERS;

FEEDFORWARD AMPLIFIER; FEEDFORWARD CAPACITOR; SHORT CHANNEL EFFECTS;

LSI CIRCUITS;

EID: 0030397170     PISSN: 09168524     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (16)

1. M. Kakumu, Process and device technologies of CMOS devices for low-voltage operation, IEICE Trans. Electron, vol. E76-C, no. 5, pp. 672-680, May 1993.
2. S. Horiguchi, T. Tsukahara, and H. Fukuda, Low-power LSI circuit technologies for portable terminal equipment, IEICE Trans. Electron, vol. E78-C, no. 12, pp. 1655-1667, Dec., 1995.
3. P. C. Yu and H. S. Lee, A high-swing 2 V CMOS operational amplifier with gain enhancement using a replica amplifier, ISSCC digest of Technical Papers, pp. 1 loll 7, Feb. 1993.
4. M. Yotsuyanagi, H. Hasegawa, M. Yamaguchi, M. Ishida, and S. Sone, A 2V, lOb, 20Msample/s mixed-mode subranging CMOS A/D converter, ISSCC digest of Technical Papers, pp. 282-283, 1995.
5. H. Hasegawa, M. Yotsuyanagi, M. Satoh, S. Kishi, M. Ishida, and M. Yamaguchi, A 1.5-V 8-b, 8-mW, BiCMOS video A/D converter, ISSCC digest of Technical Papers, pp. 322-323, Feb. 1996.
6. Y. Matsuya and J. Yamada, IV power supply, 384 ks/s, lOb, A/D and D/A converters with swing-suppression noise shaping, ISSCC digest of Technical Papers, pp. 192 -193, Feb., T994.
7. M. Miyamoto, T. Ishii, R. Nagai, T. Nishida, and K. Seki, 0.3-/m mixed analog/digital CMOS technology for low voltage operation, IEEE 1993 Custom Integrated Circuits Conference, 24.4. 1, May 1993.
8. T. Matsuura, K. Yano, M. Hiraki, Y. Sasaki, M. Miyamoto, T. Ishii, R. Nagai, T. Nishida, K. Seki, E. Imaizumi, T. Anbo, N. Sumi, and K. Rikino, 1.2-V mixed analog/digital circuits using 0.3-//m CMOS LSI technology, ISSCC digest of Technical Papers, pp. 250251, Feb. 1994.
9. S. H. Lewis and P. R. Gray, A pipelined 5-M sample/s 9-bit analog-to digital converter, IEEE J. Solid-State Circuits, vol. SC-22, no. 6, Dec. 1987, pp. 954-961.
10. N. Sumi, K. Rikino, T. Matsuura, K. Seki, and K. Yano, A study of low-voltage multiplier, Proceedings of the 1994 IEICE Spring Conference C-629, March, 1994.
11. N. Levy and J. P~. Leonard, 1995 END's DSP-Chip Directory, EDN pp. 64-91, May II, 1995.
12. B. Y. Kamath, R. G. Meyer, and P. R. Gray, Relationship between frequency response and settling time of operational amplifiers, IEEE J. Solid-State Circuits, vol. SC-9, no. 6, pp. 347-352, Dec. 1974.
13. P. E. Allen and D. R. Holberg, CMOS Analog Circuit Design, chapter 8 Holt, Rinehart and Winston, Inc. 1987.
14. H. C. Yang and D. J. Allstot, Considerations for fast settling operational amplifiers, IEEE Trans. Circuits and Syst. vol. 37, no. 3, pp. 326-334, March 1990.
15. K. Yano, T. Yamanaka, T. Nishida, M. Saitoh, K. Shimohigashi, and A. Shimizu, A 3.8-ns CMOS 16X 16 multiplier using complementary pass transistor logic, 1989 Custom Integrated Circuits Conference, May 1989.
16. Y. Sasaki, K. Yano, M. Hiraki, K. Rikino, M. Miyamoto, T. Matsuura, T. Nishida, and K. Seki, Pass transistor based gate array architecture, Symposium on VLSI Circuit Digest of Technical Papers, June 1995.