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Volumn , Issue , 1989, Pages

A 3.8ns CMOS 16×16 multiplier using complementary pass transistor logic

Author keywords

[No Author keywords available]

Indexed keywords

COMPLEMENTARY PASS-TRANSISTOR LOGIC; CRITICAL PATHS; GAAS; INPUT CAPACITANCE; INPUT/OUTPUT; PASS-TRANSISTOR LOGIC; SUPPLY VOLTAGES;

EID: 84869398058     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CICC.1989.56843     Document Type: Conference Paper
Times cited : (9)

References (9)


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.