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Volumn , Issue , 1989, Pages
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A 3.8ns CMOS 16×16 multiplier using complementary pass transistor logic
a a a a a a
a
HITACHI LTD
(Japan)
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Author keywords
[No Author keywords available]
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Indexed keywords
COMPLEMENTARY PASS-TRANSISTOR LOGIC;
CRITICAL PATHS;
GAAS;
INPUT CAPACITANCE;
INPUT/OUTPUT;
PASS-TRANSISTOR LOGIC;
SUPPLY VOLTAGES;
INTEGRATED CIRCUITS;
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EID: 84869398058
PISSN: 08865930
EISSN: None
Source Type: Conference Proceeding
DOI: 10.1109/CICC.1989.56843 Document Type: Conference Paper |
Times cited : (9)
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References (9)
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