Pass transistor based gate array architecture

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 1995, Pages 123-124

  Sasaki, Yasuhiko ^a   Yano, Kazuo ^a   Hiraki, Mitsuru ^a   Rikino, Kunihito ^a   Miyamoto, Masafumi ^a   Matsuura, Tatsuji ^a   Nishida, Takashi ^a   Seki, Koichi ^a  

^a HITACHI LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ARRAYS; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; GATES (TRANSISTOR); LOGIC CIRCUITS; LOGIC GATES; MULTIPLYING CIRCUITS; RANDOM ACCESS STORAGE;

GATE ARRAY ARCHITECTURE; PASS TRANSISTOR LOGIC;

LOGIC DESIGN;

EID: 0029488510     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (2)