Chip-planning, placement, and global routing of macro/custom cell integrated circuits using simulated annealing.

Proceedings - Design Automation Conference

Volumn , Issue , 1988, Pages 73-80

  Sechen, Carl ^a  

^a YALE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER PROGRAMMING -- ALGORITHMS; COMPUTER SIMULATION;

CHIP-PLANNING; CIRCUIT-AREA REDUCTIONS; GLOBAL ROUTING; PLACEMENT; SIMULATED ANNEALING;

INTEGRATED CIRCUITS;

EID: 0024142707     PISSN: 01467123     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (28)