Latchup-aware placement and parasitic-bounded routing of custom analog cells

Volumn , Issue , 1993, Pages 415-421

  Basaran, Bulent ^a   Rutenbar, Rob A ^a   Carley, L Richard ^a  

^a CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CMOS INTEGRATED CIRCUITS; CONSTRAINT THEORY; CROSSTALK; ELECTRIC NETWORK TOPOLOGY; INTEGRATED CIRCUIT LAYOUT; OPTIMIZATION;

CUSTOM ANALOG CELLS; LATCHUP-AWARE PLACEMENT; PARASITIC BOUNDED ROUTING;

LINEAR INTEGRATED CIRCUITS;

EID: 0027876719     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (15)