Timing Constraints for Wave Pipelined Systems

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 13, Issue 8, 1994, Pages 987-1004

  Gray, C Thomas ^a   Liu, Wentai ^b   Cavin, Ralph K ^b  

^a IBM   (United States)

^b NORTH CAROLINA STATE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CMOS INTEGRATED CIRCUITS; COMBINATORIAL CIRCUITS; CONSTRAINT THEORY; DELAY CIRCUITS; INTEGRATED CIRCUIT LAYOUT; LINEAR PROGRAMMING; MATHEMATICAL MODELS; PERFORMANCE; PIPELINE PROCESSING SYSTEMS; SYSTEMS ANALYSIS; TIMING CIRCUITS;

CLOCK PERIOD; CLOCK SKEW; GLOBAL CLOCK LATENCY; LOGIC DELAYS; TIMING CONSTRAINTS; WAVE PIPELINED SYSTEMS;

COMPUTER AIDED LOGIC DESIGN;

EID: 0028484138     PISSN: 02780070     EISSN: 19374151     Source Type: Journal    
DOI: 10.1109/43.298035     Document Type: Article

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