A Bipolar Population Counter Using Wave Pipelining to Achieve 2.5 x Normal Clock Frequency

IEEE Journal of Solid-State Circuits

Volumn 27, Issue 5, 1992, Pages 745-753

  Wong, Derek C ^a   De Micheli, Giovanni ^a   Flynn, Michael J ^a   Huston, Robert E ^b  

^a STANFORD UNIVERSITY   (United States)

^b LTX Corporation Trillium Division ^*  (United States)

Author keywords

computer design; computer aided design; digital circuits; fine tuning; hardware; maximal rate pipelining; power optimization; rough tuning; Wave pipelining

Indexed keywords

COMPUTER AIDED DESIGN; INTEGRATED CIRCUITS, VLSI - LAYOUT; LOGIC CIRCUITS, COMBINATORIAL; LOGIC DESIGN; OPTIMIZATION;

BIPOLAR POPULATION COUNTER; CURRENT MODE LOGIC; FINE TUNING; MAXIMAL-RATE PIPELINING; ROUGH TUNING; WAVE PIPELINING;

COMPUTER SYSTEMS, DIGITAL;

EID: 0026869432     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/4.133161     Document Type: Article

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