Some optimal schemes for ALU implementation in VLSI technology

Proceedings - Symposium on Computer Arithmetic

Volumn , Issue , 1985, Pages 2-8

  Oklobdzija, Vojin G ^a   Barnes, Earl R ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

VLSI CIRCUITS;

CARRY CHAINS; CARRY PROPAGATION; EFFICIENT SCHEMES; MOS TECHNOLOGY; OPTIMAL SCHEME; PARALLEL ADDERS; REGULAR STRUCTURE; VLSI TECHNOLOGY;

LOGIC CIRCUITS;

EID: 85065824578     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ARITH.1985.6158969     Document Type: Conference Paper

References (9)

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2. M. Lehman, A Comparative Study of Propagation Speed-up Circuits in Binary Arithmetic Units, Information Processing, 1962, Elsevier-North Holand, Amsterdam, 1963, p. 671.
3. M. Lehman and N. Burla, Skip Techniques for High-Speed Carry-Propagation in Binary Arithmetic Units, IRE Transactions on Electronic Computers, December 1961, p. 691.
4. L.P. Morgan and D.B. Jarvis, Transistor Logic Using Current Switching and Routing Techniques and its Application to a Fast "Carry" Propagation Adder, Proc. IEE, pt. B, Vol. 106, p. 467, September 1969.
5. Kai Hwang, Computer Arithmetic: Principles Architecture and Design, John Wiley and Sons, 1979.
6. S. Ong and D.E. Atkins, A Comparison of ALU Structures for VLSI Technology, Proc. of the 6th Symposium on Computer Arithmetic, June 20-22, 1983, Aarhus University, Aarhus, Denmark.
7. Robert K. Montoye, P.W. Cook, Automatically Generated Area., Power, and Delay Optimized ALUs, IEEE ISSCC Digest of Technical Papers, February 23-24, 1983, New York.
8. A. Bilgory and D.D. Gajski, Automatic Generation of Cells for Recurrence Structures, Proc. of 18th Design Automation Conference, Nashville, Tennessee 1981.
9. V.F. Demyanov, V.N. Malozemov, Vvedenie v Minimaks, Izdatelstvo Nauka, Fiziko-Matematicheskoi Literaturi, Moskva 1972.