0.4μm 1.4ns 32b dynamic adder using non-precharge multiplexers and reduced precharge voltage technique

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 1995, Pages 9-10

  Inoue, Atsuki ^a   Kawabe, Yukihito ^a   Asada, Yoshimi ^a   Ando, Satoshi ^a  

^a FUJITSU LABORATORIES LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; DELAY CIRCUITS; INTEGRATED CIRCUIT LAYOUT; LEAKAGE CURRENTS; LOGIC DESIGN; LOGIC GATES; MULTIPLEXING EQUIPMENT; TRANSISTORS; VOLTAGE CONTROL; WAVEFORM ANALYSIS;

CMOS TECHNOLOGY; DYNAMIC ADDER; NON-PRECHARGE MULTIPLEXERS; PARASITIC CAPACITANCE; REDUCED PRECHARGE VOLTAGE TECHNIQUE;

ADDERS;

EID: 0029487720     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (2)