Tradeoff literals against support for logic synthesis of LUT-based FPGAs

IEE Proceedings: Computers and Digital Techniques

Volumn 143, Issue 2, 1996, Pages 111-119

  Lu, A ^a   Dagless, E ^a   Saul, J ^a  

^a UNIVERSITY OF BRISTOL   (United Kingdom)

Author keywords

Field progranvnable gate arrays; Look up tables; Technology mapping

Indexed keywords

ALGORITHMS; BOOLEAN FUNCTIONS; COMPUTATIONAL COMPLEXITY; COMPUTER NETWORKS; INFORMATION TECHNOLOGY; OPTIMIZATION;

BOOLEAN NETWORK; FIELD PROGRAMMABLE GATE ARRAYS; FUNCTIONAL DECOMPOSITION; LOGIC SYNTHESIS METHOD; TECHNOLOGY MAPPING;

TABLE LOOKUP;

EID: 0030110591     PISSN: 13502387     EISSN: None     Source Type: Journal    
DOI: 10.1049/ip-cdt:19960197     Document Type: Article

References (21)

1. BROWN, S.D., FRANCIS, R.J., ROSE, }., and VRANESIC, Z.G.: 'Field programmable gate arrays' (Kluwer Academic Publishers, 1992)
2. MURGAI, R., SHENOY, N., BRAYTON, R.K., and SANGIOVANNI-VINCENTELLI, A.: 'Improved logic synthesis algorithms for table look up architectures'. Proceedings of the IEEE international conference on computer aided design, IEEE Computer Society Press, 1991, pp. 564-567
3. SAWKAR, P., and THOMAS, D.: 'Area and delay mapping for table-look-up based field programmable gate arrays '. Proceedings of the 29th desien automation conference, IEEE Computer Society Press, June 1992, pp. 368-373
4. FILO, D., CHIH-YUAN YANG, J., MAILHOT, F., and DE MICHELI, G.: Technology mapping for a two-output RAMbased field programmable gate array'. Proceedings of the European Design automation Conference, IEEE Computer Society Press, February 1991, pp. 534-538
5. FRANCIS, R.J., ROSE, J., and CHUNG, K.: 'Chortle-erf: fast technology mapping for lookup table based FPCAs'. Proceedings of the 28th Design automation Conference, 1991, pp. 227-233
6. HILL, D., and DETJENS, E.: 'FPGA design principles (a tutorial)'. Proceedings of the 29th design automation conference, IEEE Computer Society Press, June 1992, pp. 45-46
7. BRAYTON, R., RUDELL, R., SANGIOVANNI-VINCENTELLI, A., and WANG, A.: 'MIS: multiple-level logic optimisation system', IEEE Trans., 1987, CAD-6, (6), pp. 1062-1081
8. BOSTIC, D., HACHTEL, G., JACOBY, R., LIGHTNER, M.. MOCEYUNAS, P., MORRISON, C., and RAVENSCROFT, D.: 'The boulder optimal logic design system'. Proceedings of the international conference on computer-aided design, IEEE Computer Society Press, November 1987, pp. 62-69
9. BRAYTON, R.K., HACHTEL, G.D., and SANGIOVANNIVINCENTELLI, A.L.: 'Multilevel losic synthesis', Proc. IEEE, 1990, 78, (2), pp. 264-300
10. FUJITA, M., and MATSUNAGA, Y.: 'Multi-level logic minimisation based on minimal support and its application to the minimization of look-up table type FPGAs'. Proceedings of the IEEE International Conference on Computer aided design, 1991, pp. 560-563
11. TING-TING HWANG , OWENS, R.M., IRWIN, M.J., and WANG, K.H.: 'Logic synthesis for field-programmable gate arrays', IEEE Trans. Compiit.-Aided Des. Integr. Circuits Syst., 1994, 13, (10), pp. 1280-1287
12. LAI, Y., PAN, K.R., and PEDRAM, M.: 'FPGA synthesis using function decomposion'. Proceedings of International Conference on Computer design: VLSI in computers and processors, October 1994, pp. 30-35
13. LU, A., SAUL, J., and DAGLESS, E.: 'Architecture oriented logic optimisation for lookup table based FPGAs'. Proceedings of International Conference on Computer design: VLSI in computers and processors, October 1994, pp. 26-29
14. WURTH, B., KCKL, K., and ANTREICH, K.: 'Functional multiple-output decomposition: theory and an implicit algorithm'. Proceedings of 32th Design automation Conference, San Francisco, June 1995, pp. 54-59
15. BRAYTON, R.K., HACHTEL, G.D., MCMULLEN, C., and SANGIOVANNI-VINCENTELLI, A.: 'Logic minimization algorithms for VLSI synthesis' (Kluwer Academic Publishers, 1984)
16. BRAYTON, R., and MCMULLEN, C: 'The decomposition and factorisation of Boolean expressions'. Proceedings of international symposium on Circuits and systems, Rome, May 1982, pp. 49-54
17. RUDELL, R.: 'Logic synthesis for VLSI design'. PhD thesis, University of California, Berkeley, 1989
18. SENTOVICH, E.M., SINGH, K.J., MOON, C., SAVOJ, H., BRAYTON, R.K., and SANGIOVANNI-VINCENTELLI, A.: 'Sequential circuit design using synthesis and Optimisation'. Proceedings of the international conference on computer design, IEEE Computer Society Press, October 1992, pp. 328-333
19. XILINX INC.: 'The programmable gate array data book' (Xilinx, San Jose, CA, 1994)
20. CHAN, P.K., SCHLAG, M., and ZIEN, J.: 'On routability prediction for field-programmable gate arrays'. Proceedings of 30th Design automation Conference, June 1993, pp. 326-330
21. SCHLAG, M., KONG, J., and CHAN, P.: 'Routability-driven technology mapping for lookup table-based FPGAs', IEEE Trans. Compul.-Aided DCS. Integr. Circuits Svst., January 1994, 13, (1), pp. 13-26