Area and delay mapping for table-look-up based field programmable gate arrays

Proceedings - Design Automation Conference

Volumn , Issue , 1992, Pages 368-373

  Sawkar, Prashant ^a   Thomas, Donald ^a  

^a CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; LOGIC GATES; OPTIMIZATION; TABLE LOOKUP;

SHANNON EXPANSION; TECHNOLOGY MAPPING;

INTEGRATED CIRCUIT MANUFACTURE;

EID: 0026997842     PISSN: 01467123     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)