Validation of compact conduction models of BGA under an expanded boundary condition set

InterSociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems, ITHERM

Volumn 2002-January, Issue , 2002, Pages 99-105

  Karimanal, K V ^a   Ahmed, G R ^b  

^a ANSYS INC   (United States)

^b Ceyba Inc   (United States)

Author keywords

Boundary conditions; Lead; Microelectronics; Network topology; Packaging; Predictive models; Resistors; Steady state; Temperature distribution; Testing

Indexed keywords

LEAD; MICROELECTRONICS; PACKAGING; RESISTORS; TEMPERATURE DISTRIBUTION; TESTING;

BOUNDARY CONDITION INDEPENDENCES; CONDUCTION MODELING; CONDUCTION MODELS; DIE TEMPERATURES; NETWORK TOPOLOGY; PREDICTIVE MODELS; STEADY STATE; STEADY-STATE CONDITION;

BOUNDARY CONDITIONS;

EID: 0013284256     PISSN: 19363958     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ITHERM.2002.1012444     Document Type: Conference Paper

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