A high-performance Sigma-Delta ADC for ADSL applications in 0.35μm CMOS digital technology

Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems

Volumn 1, Issue , 2001, Pages 501-504

  Del Rio, R ^a   De La Rosa, J M ^a   Medeiro, F ^a   Perez Verdu B ^a   Rodriguez Vazquez A ^a  

^a CSIC   (Spain)

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG PERFORMANCE; CASCADE ARCHITECTURE; CMOS DIGITAL TECHNOLOGY; DIGITAL TECHNOLOGIES; DYNAMIC RANGE; MULTI-BIT QUANTIZERS; OVER SAMPLING RATIO; SIGMA DELTA MODULATOR; SIGMA-DELTA; SINGLE-BIT; SUBSTRATE COUPLINGS; TECHNOLOGY ISSUES;

DIGITAL SIGNAL PROCESSING;

MODEMS;

EID: 0009597505     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)

1. F. Medeiro, B. Pérez-Verdú and A. Rodríguez- Vázquez: "A 13-bit, 2.2-MS/s, 55-mW Multibit Cascade ∑Δ Modulator in CMOS 0.7-μm Single-Poly Technology," IEEE J. of Solid-State Circuits, vol. 34, pp. 748-760, June 1999.
2. A. M. Marques, V. Peluso, M. S. J. Steyaert, and W. Sansen: "A 15-b Resolution 2-MHz Nyquist Rate Δ∑ ADC in a 1-μm CMOS Technology," IEEE J. of Solid-State Circuits, vol. 33, pp. 1065-1075, July 1998.
3. Y. Geerts, A. Marques, M. Steyaert, and W. Sansen: "A 3.3-V, 15-bit, Delta-Sigma ADC with a Signal Bandwidth of 1.1 MHz for ADSL Applications," IEEE J. of Solid-State Circuits, vol. 34, pp. 927-936, July 1999.
4. A.R. Feldman, B. E. Boser, and P. R. Gray: "A 13-Bit, 1.4-MS/s Sigma-Delta Modulator for RF Baseband Channel Applications," IEEE J. of Solid-State Circuits, vol. 33, pp. 1462-1469, October 1998.
5. B. Brandt and B. A. Wooley: "A 50-MHz Multibit ∑Δ Modulator for 12-b 2-MHz A/D Conversion," IEEE J. of Solid-State Circuits, vol. 26, pp. 1746-1756, Dec. 1991.
6. I. Fujimori, et al.: "A 90dB SNR, 2.5MHz Output Rate ADC using Cascaded Multibit Delta-Sigma Modulation at 8x Oversampling Ratio," IEEE J. of Solid-State Circuits, vol. 35, pp. 1820-1828, Dec. 2000. (Pubitemid 32138752)
7. R. del-Rio, F. Medeiro, B. Pérez-Verdú, and A. Rodríguez-Vázquez: "High-Order Cascade Multibit ∑Δ Modulators for xDSL Applications," Proc. Int. Symp. Circuits and Systems, Vol.2, pp. 37-40, May 2000.
8. F. Medeiro, B. Pérez-Verdú, and A. Rodriguez- Vázquez: Top-Down Design of High-Petformance Modulators, Kluwer Academic Publishers, 1999.
9. R. del Rio, F. Medeiro, J.M. de la Rosa, B. Pérez-Verdú, and A. Rodriguez-Vázquez: "A 14-bit 4-MS/s Multi-bit Cascade SD Modulator in CMOS 0.35-μm Digital Technology," Proc. Design of Integrated Circuits and Systems Conf., pp. 133-138, November 2000.
10. X. Aragonés, et al.: Analysis and Solutions for Switching Noise Coupling in Mixed-Signal ICs, Kluwer Academic Publishers, 1999.