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Volumn 31, Issue 2, 1996, Pages 230-239
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A 965-Mb/s 1.0-μm standard CMOS twin-pipe serial/parallel multiplier
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Author keywords
[No Author keywords available]
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Indexed keywords
ADDERS;
CMOS INTEGRATED CIRCUITS;
COMPUTER ARCHITECTURE;
DATA COMMUNICATION SYSTEMS;
DIGITAL ARITHMETIC;
INTEGRATED CIRCUIT LAYOUT;
PARALLEL PROCESSING SYSTEMS;
HIGH SPEED BUS COMMUNICATION;
PARALLEL COEFFICIENT;
SERIAL DATA;
SERIAL PARALLEL MULTIPLIER;
MULTIPLYING CIRCUITS;
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EID: 0030083065
PISSN: 00189200
EISSN: None
Source Type: Journal
DOI: 10.1109/4.488000 Document Type: Article |
Times cited : (11)
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References (7)
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