Use of multiplier blocks to reduce filter complexity

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 4, Issue , 1994, Pages 263-266

  Dempster, A G ^a   Macleod, M D ^a  

^a UNIVERSITY OF CAMBRIDGE   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; ALGORITHMS; DIGITAL ARITHMETIC; ELECTRIC NETWORK TOPOLOGY; FREQUENCY DOMAIN ANALYSIS; FREQUENCY MULTIPLYING CIRCUITS; INTEGRATED CIRCUITS; OPTIMAL CONTROL SYSTEMS; OPTIMIZATION; TABLE LOOKUP;

CANONIC SIGNED DIGIT REPRESENTATION; MINIMUM ADDER GRAPH ALGORITHMS;

DIGITAL FILTERS;

EID: 0028585206     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (11)