General algorithms for reduced-adder integer multiplier design

Electronics Letters

Volumn 31, Issue 21, 1995, Pages 1800-1802

  Dempster, A G ^a   Macleod, M D ^b  

^a UNIVERSITY OF WESTMINSTER   (United Kingdom)

^b UNIVERSITY OF CAMBRIDGE   (United Kingdom)

Author keywords

Digital circuits; Multiplying circuits

Indexed keywords

ADDERS; ALGORITHMS; COMPUTER HARDWARE; COMPUTER SOFTWARE; GRAPHIC METHODS;

SHIFT-AND-ADD MULTIPLICATION; SUBEXPRESSION ELIMINATION;

MULTIPLYING CIRCUITS;

EID: 0029388388     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:19951242     Document Type: Article

References (13)

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