Generalized reasoning scheme for redundancy addition and removal logic optimization

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2001, Pages 391-395

  Espejo, J A ^a   Entrena, L ^a   San Millan, E ^a   Olias, E ^a  

^a UNIVERSIDAD CARLOS III DE MADRID   (Spain)

Author keywords

[No Author keywords available]

Indexed keywords

BASIC NODE; LOGIC OPTIMIZATION; REASONING SCHEMES; STRUCTURAL REDUNDANCY; STRUCTURAL TRANSFORMATION;

EXHIBITIONS;

REDUNDANCY;

EID: 0006993644     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2001.915054     Document Type: Conference Paper

References (9)

1. K.-T. Cheng, L. Entrena. "Sequential Logic Optimization by Redundancy Addition and Removal". Proc. 1CCAD'93
2. S.-C. Chang, K.-T. Cheng, N.-S. Woo, M. Marek-Sadowska. "Post-layout logic restructuring using alternative wires". IEEE Transactions on CAD, vol. 16, n. 6
3. S. C. Chang, M. Marek-Sadowska, K.-T. Cheng. "Perturb and Simplify: Multilevel Boolean Network Optimizer". IEEE Transactions on CAD, vol. 15, no 12
4. W. Kunz, P. Menon. "Multi-Level Logic Optimization by Implication Analysis". Proc. ICCAD-94, p. 6-13. Nov. 1994
5. W. Kunz, D. Stoffel. "Reasoning in Boolean Networks: logic synthesis and verification using testing techniques". Ed. Kluwer Academic Publishers, 1997
6. S. C. Chang, L. P. Van Ginnekan, M. Marek-Sadowska. "Fast Boolean Optimization by Rewiring". Proc. ICCAD'96.
7. "SIS: A System for Sequential Circuit Synthesis" Report M92/41, University of California, Berkeley, May. 1992.
8. L. Entrena, J. A. Espejo, E. Olías, J. Uceda. "Timing optimization by and Improved Redundancy Addition and Removal Technique". Proc. EURO-DAC'96
9. J. A. Espejo, L. Entrena, E. San Millán, E. Olías. "Functional extension for structural logic optimization techniques". Proc. ASP-DAC'01. January, 2001.