Quality estimation of test vectors and functional validation procedures based on fault and error models

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 1998, Pages 955-956

  Riesgo, T ^a   Torroja, Y ^a   De La Torre, E ^a   Uceda, J ^a  

^a UNIVERSIDAD POLITÉCNICA DE MADRID   (Spain)

Author keywords

[No Author keywords available]

Indexed keywords

ERROR MODEL; FAULT MODEL; FUNCTIONAL VALIDATION; QUALITY ESTIMATION; TEST VECTORS;

ESTIMATION;

EID: 28344439141     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.1998.655986     Document Type: Conference Paper

References (6)

1. PRENDA, ASIC Design Methodologies, edited by UPM/DIE (Spain), November 1996.
2. B. Bennetts, "Test Synthesis: Towards Higher Levels of Abstraction", Proc. 2nd Archimedes Workshop on Synthesis of Testable Circuits, Barcelona, February 1995.
3. P. Camurati, P. Prinetto, "Formal Verification of Hardware Correctness: Introduction and Survey of Current Research", IEEE Computer, pp. 8-19, July 1988.
4. IEEE, IEEE Standard VHDL Language Reference Manual. IEEE Std 1076-1993, IEEE, 1993.
5. T. Riesgo, J. Uceda, "A Fault Model for VHDL Descriptions at the Register Transfer Level", Proc. of EURO-DAC with EURO-VHDL'96, Geneva (Switzerland), September 1996.
6. T. Riesgo, Y. Torroja, C. López, J. Uceda, "Estimation of the Quality of Design Validation Experiments Based on Error Models", Proc. of VHDL Users'Forum in Europe, Toledo (Spain), April 1997.