DSP processor/compiler co-design: a quantitative approach

Proceedings of the International Symposium on System Synthesis

Volumn , Issue , 1996, Pages 108-113

  Zivojnovic, Vojin ^a   Pees, Stefan ^a   Schlaeger, Christian ^a   Willems, Markus ^a   Schoenen, Rainer ^a   Meyr, Heinrich ^a  

^a RWTH AACHEN UNIVERSITY   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; PROGRAM COMPILERS; PROGRAM PROCESSORS; REDUCED INSTRUCTION SET COMPUTING; STANDARDS;

FAST PROCESSOR SIMULATION; FORMAL MACHINE SPECIFICATION; STANDARD PROCESSOR SIMULATORS;

DIGITAL SIGNAL PROCESSING;

EID: 0030391973     PISSN: 10801820     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (15)