Architecture evaluation based on the datapath structure and parallel constraint

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn , Issue , 1997, Pages 503-508

  Yamaguchi, Masayuki ^a   Yamada, Akihisa ^a   Nakaoka, Toshihiro ^a   Kambe, Takashi ^a  

^a SHARP CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; CONSTRAINT THEORY; ELECTRIC NETWORK SYNTHESIS; ESTIMATION; PROGRAM PROCESSORS; REDUCED INSTRUCTION SET COMPUTING;

DATAPATH STRUCTURES; PARALLEL CONSTRAINTS;

DIGITAL SIGNAL PROCESSING;

EID: 0030646103     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (13)