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Volumn 48, Issue 7, 2001, Pages 675-683

A low-complexity combinatorial RNS multiplier

Author keywords

Digital arithmetic; Multiplication; Residue arithmetic; Very large scale integration

Indexed keywords


EID: 0002904957     PISSN: 10577130     EISSN: None     Source Type: Journal    
DOI: 10.1109/82.958337     Document Type: Article
Times cited : (24)

References (15)
  • 2
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    • 32 pp. 50-62 May 1984.
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    • IEEE Trans. Comput. Vol. C
    • Taylor, F.1
  • 3
    • 33749950483 scopus 로고    scopus 로고
    • Applications of residue number systems to complex digital filters in
    • 15th Asilomar Conf. Circuits Systems and Computers 1981 pp. 70-74.
    • S. H. Leung Applications of residue number systems to complex digital filters in Proc. 15th Asilomar Conf. Circuits Systems and Computers 1981 pp. 70-74.
    • Proc.
    • Leung, S.H.1
  • 5
    • 0019069143 scopus 로고    scopus 로고
    • Implementation of multiplication modulo a prime number with applications to number theoretic transforms
    • 29 pp. 899-905 Oct. 1980.
    • G. A. Jullien Implementation of multiplication modulo a prime number with applications to number theoretic transforms IEEE Trans. Comput. vol. C-29 pp. 899-905 Oct. 1980.
    • IEEE Trans. Comput. Vol. C
    • Jullien, G.A.1
  • 6
    • 0026679901 scopus 로고    scopus 로고
    • Novel approaches to the design of VLSI RNS multipliers
    • vol. 39 pp. 52-57 Jan. 1992.
    • D. Radhakrishnan and Y. Yuan Novel approaches to the design of VLSI RNS multipliers IEEE Trans. Circuits Syst. II vol. 39 pp. 52-57 Jan. 1992.
    • IEEE Trans. Circuits Syst. II
    • Radhakrishnan, D.1    Yuan, Y.2
  • 7
    • 0029308383 scopus 로고    scopus 로고
    • Fast combinatorial RNS processors for DSP applications
    • vol. 44 pp. 624-633 May 1995.
    • E. D. DiClaudio F. Piazza and G. Orlandi Fast combinatorial RNS processors for DSP applications IEEE Trans. Comput. vol. 44 pp. 624-633 May 1995.
    • IEEE Trans. Comput.
    • Diclaudio, E.D.1    Piazza, F.2    Orlandi, G.3
  • 8
  • 9
    • 0029405986 scopus 로고    scopus 로고
    • A systolic architecture for modulo multiplication
    • vol. 42 pp. 725-729 Nov. 1995.
    • K. M. Elleithy and M. A. Bayoumi A systolic architecture for modulo multiplication IEEE Trans. Circuits Syst. II vol. 42 pp. 725-729 Nov. 1995.
    • IEEE Trans. Circuits Syst. II
    • Elleithy, K.M.1    Bayoumi, M.A.2
  • 10
    • 0033356431 scopus 로고    scopus 로고
    • Multifunction architectures for RNS processors
    • vol. 46 pp. 1041-1054 Aug. 1999.
    • V Paliouras and T. Stouraitis Multifunction architectures for RNS processors IEEE Trans. Circuits Syst. II vol. 46 pp. 1041-1054 Aug. 1999.
    • IEEE Trans. Circuits Syst. II
    • Paliouras, V.1    Stouraitis, T.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.