A VLSI design methodology for RNS full adder-based inner product architectures

IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing

Volumn 44, Issue 4, 1997, Pages 315-318

  Soudris, D J ^a   Paliouras, V ^b   Stouraitis, T ^b   Goutis, C E ^b  

^a DEMOCRITUS UNIVERSITY OF THRACE   (Greece)

^b UNIVERSITY OF PATRAS   (Greece)

Author keywords

Bit level design methodology; Inner product processor; Residue number system

Indexed keywords

ADDERS; ALGORITHMS; COMPUTER AIDED LOGIC DESIGN; COMPUTER ARCHITECTURE; CONFORMAL MAPPING; DIGITAL SIGNAL PROCESSING; PARALLEL PROCESSING SYSTEMS; ROM;

BIT LEVEL DESIGN METHODOLOGY; RESIDUE NUMBER SYSTEMS (RNS);

VLSI CIRCUITS;

EID: 0031121242     PISSN: 10577130     EISSN: None     Source Type: Journal    
DOI: 10.1109/82.566648     Document Type: Article

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