High speed FPGA-based implementations of delayed-LMS filters

Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology

Volumn 39, Issue 1-2 SPEC.ISS., 2005, Pages 113-131

  Yi, Y ^a   Woods, R ^a   Ting, L K ^b   Cowan, C F N ^a  

^a QUEEN'S UNIVERSITY BELFAST   (United Kingdom)

^b Intel Microelectronics ^*  (Malaysia)

Author keywords

Adaptive filtering; Delayed LMS filters; FPGA; Hardware sharing; Retiming technique

Indexed keywords

ADAPTIVE FILTERING; ALGORITHMS; DELAY CIRCUITS; DIGITAL SIGNAL PROCESSING; HARDWARE; MICROPROCESSOR CHIPS; NATURAL FREQUENCIES;

DELAYED LMS FILTERS; HARDWARE SHARING; LEAST MEAN SQUARE (LMS); RETIMING TECHNIQUE;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 9144220330     PISSN: 13875485     EISSN: None     Source Type: Journal    
DOI: 10.1023/B:VLSI.0000047275.54691.be     Document Type: Conference Paper

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