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Volumn 2002-January, Issue , 2002, Pages 139-145
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High sampling rate retimed DLMS filter implementations in Virtex-II FPGA
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Author keywords
Circuits; Computer architecture; Delay; Error correction; Feedback loop; Field programmable gate arrays; Finite impulse response filter; Least squares approximation; Pipeline processing; Sampling methods
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Indexed keywords
ALGORITHMS;
COMPUTER ARCHITECTURE;
DELAY CIRCUITS;
ERROR CORRECTION;
FIELD PROGRAMMABLE GATE ARRAYS (FPGA);
FIR FILTERS;
IMPULSE RESPONSE;
INTEGRATED CIRCUIT DESIGN;
LEAST SQUARES APPROXIMATIONS;
NETWORKS (CIRCUITS);
SIGNAL PROCESSING;
DELAY;
EFFICIENT IMPLEMENTATION;
FEED-BACK LOOP;
HIGH SAMPLING RATES;
PIPELINE PROCESSING;
PIPELINED ARCHITECTURE;
PROCESSING DELAY;
SAMPLING METHOD;
PIPELINE PROCESSING SYSTEMS;
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EID: 78649273312
PISSN: 15206130
EISSN: None
Source Type: Conference Proceeding
DOI: 10.1109/SIPS.2002.1049699 Document Type: Conference Paper |
Times cited : (13)
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References (7)
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