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Volumn 2002-January, Issue , 2002, Pages 139-145

High sampling rate retimed DLMS filter implementations in Virtex-II FPGA

Author keywords

Circuits; Computer architecture; Delay; Error correction; Feedback loop; Field programmable gate arrays; Finite impulse response filter; Least squares approximation; Pipeline processing; Sampling methods

Indexed keywords

ALGORITHMS; COMPUTER ARCHITECTURE; DELAY CIRCUITS; ERROR CORRECTION; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); FIR FILTERS; IMPULSE RESPONSE; INTEGRATED CIRCUIT DESIGN; LEAST SQUARES APPROXIMATIONS; NETWORKS (CIRCUITS); SIGNAL PROCESSING;

EID: 78649273312     PISSN: 15206130     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SIPS.2002.1049699     Document Type: Conference Paper
Times cited : (13)

References (7)
  • 1
    • 0024733684 scopus 로고
    • The LMS algorithm with delayed coefficient adaptation
    • Sept.
    • G. Long, F. Ling, and J.G. Proakis, "The LMS algorithm with delayed coefficient adaptation," IEEE Trans. on ASSP, vol. 37, pp. 1397-1405, Sept. 1989.
    • (1989) IEEE Trans. on ASSP , vol.37 , pp. 1397-1405
    • Long, G.1    Ling, F.2    Proakis, J.G.3
  • 5
    • 0031147318 scopus 로고    scopus 로고
    • Architectural Synthesis of Digital Signal Processing Algorithms using IRIS
    • May
    • D Trainor, R F Woods and J V McCanny, "Architectural Synthesis of Digital Signal Processing Algorithms using IRIS", Journal of VLSI Signal Processing, Vol. 16, No 1, May 1997, pp41-56.
    • (1997) Journal of VLSI Signal Processing , vol.16 , Issue.1 , pp. 41-56
    • Trainor, D.1    Woods, R.F.2    McCanny, J.V.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.