Architectural Synthesis of Digital Signal Processing Algorithms Using "IRIS"

Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology

Volumn 16, Issue 1, 1997, Pages 41-55

  Trainor, D W ^a   Woods, R F ^a,b   Mccanny, J V ^a,c,d,e  

^a QUEEN'S UNIVERSITY BELFAST   (United Kingdom)

^b Queen's University of Belfast ^*

^c ROYAL ACADEMY OF ENGINEERING   (United Kingdom)

^d Institute of Physics

^e Integrated Silicon Systems Ltd   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER ARCHITECTURE; COMPUTER HARDWARE; COMPUTER HARDWARE DESCRIPTION LANGUAGES; PERFORMANCE; VLSI CIRCUITS;

ARCHITECTURAL SYNTHESIS SYSTEM; DIGITAL SIGNAL PROCESSING ALGORITHMS;

DIGITAL SIGNAL PROCESSING;

EID: 0031147318     PISSN: 13875485     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

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