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Volumn 24, Issue 5, 2004, Pages 20-33

PRO3: A hybrid NPU architecture

Author keywords

[No Author keywords available]

Indexed keywords

DATA STORAGE EQUIPMENT; NETWORK PROTOCOLS; PIPELINE PROCESSING SYSTEMS; QUALITY OF SERVICE; REDUCED INSTRUCTION SET COMPUTING; SEMICONDUCTOR DEVICES;

EID: 8844271771     PISSN: 02721732     EISSN: None     Source Type: Journal    
DOI: 10.1109/MM.2004.55     Document Type: Article
Times cited : (12)

References (10)
  • 2
    • 0033204142 scopus 로고    scopus 로고
    • "Packet Classification on Multiple Fields"
    • Sept
    • P. Gupta and N. McKeown, "Packet Classification on Multiple Fields," Computer Communication Rev., vol. 29, no. 4, Sept. 1999, pp. 147-160.
    • (1999) Computer Communication Rev. , vol.29 , Issue.4 , pp. 147-160
    • Gupta, P.1    McKeown, N.2
  • 3
    • 0041589403 scopus 로고    scopus 로고
    • "A Fully Programmable Memory Management System Supporting Queue Handling at Multi-Gigabit Rates"
    • ACM Press
    • G. Kornaros et al., "A Fully Programmable Memory Management System Supporting Queue Handling at Multi-Gigabit Rates," Proc. 40th Design Automation Conf. (DAC 03), ACM Press, 2003, pp. 54-59.
    • (2003) Proc. 40th Design Automation Conf. (DAC 03) , pp. 54-59
    • Kornaros, G.1
  • 6
    • 1942520327 scopus 로고    scopus 로고
    • "Packet Processing Acceleration with a 3-Stage Programmable Pipeline Engine"
    • Mar
    • I. Papaefstathiou et al., "Packet Processing Acceleration with a 3-Stage Programmable Pipeline Engine," IEEE Communication Letters, vol. 8, no. 4, Mar. 2004, pp. 183-185.
    • (2004) IEEE Communication Letters , vol.8 , Issue.4 , pp. 183-185
    • Papaefstathiou, I.1
  • 7
    • 8844240259 scopus 로고    scopus 로고
    • "A New Reference Design Development Environment for JPEG 2000 Applications"
    • B. Finch and W. Miller, "A New Reference Design Development Environment for JPEG 2000 Applications," System-on-Chip and ASIC Design Conf. (DesignCon 03), 2003, http://www.cast-inc.com/info/pr/materials/cast_JPEG2K-paper_DCon03.pdf.
    • (2003) System-on-Chip and ASIC Design Conf. (DesignCon 03)
    • Finch, B.1    Miller, W.2
  • 8
    • 0043234896 scopus 로고    scopus 로고
    • "Network Processor Performance Analysis Methodology"
    • Aug
    • S. Lakshmanamurthy et al., "Network Processor Performance Analysis Methodology," Intel Technology J., vol. 6, no. 3, Aug. 2002.
    • (2002) Intel Technology J. , vol.6 , Issue.3
    • Lakshmanamurthy, S.1
  • 9
    • 0038147509 scopus 로고    scopus 로고
    • "PowerNP Network Processor Hardware, Software and Applications"
    • March/May
    • J. Allen et al., "PowerNP Network Processor Hardware, Software and Applications," IBM J. of Systems and Development, vol. 47, nos. 2/3, March/May 2003, pp. 177-194.
    • (2003) IBM J. of Systems and Development , vol.47 , Issue.2-3 , pp. 177-194
    • Allen, J.1
  • 10
    • 8844254254 scopus 로고    scopus 로고
    • IBM PowerNP4GX Product Brief
    • IBM PowerNP4GX Product Brief, http://www.bellmicro.com/vendorshowcase/ibmmicro/downloads/NP4GX.pdf.


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.