Exploiting program branch probabilities in hardware compilation

IEEE Transactions on Computers

Volumn 53, Issue 11, 2004, Pages 1408-1419

  Styles, Henry ^a   Luk, Wayne ^a  

^a IMPERIAL COLLEGE LONDON   (United Kingdom)

Author keywords

Automatic synthesis; Dataflow architectures; Queuing theory

Indexed keywords

COMPUTER ARCHITECTURE; COMPUTER HARDWARE; COMPUTER PROGRAMMING; COMPUTER SIMULATION; FIELD PROGRAMMABLE GATE ARRAYS; OPTIMIZATION; QUEUEING NETWORKS; QUEUEING THEORY; RESOURCE ALLOCATION;

AUTOMATIC SYSNTHESIS; DATAFLOW ARCHITECTURE; HARDWARE COMPILATION; PROGRAM BRANCH PROBABILITIES;

PROGRAM COMPILERS;

EID: 8744236064     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/TC.2004.96     Document Type: Article

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