Lava and JBits: From HDL to Bitstream in Seconds

Proceedings - 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2001

Volumn , Issue , 2001, Pages 91-100

  Singh, S ^a   James Roxby, P ^a  

^a XILINX INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BINARY SEQUENCES; COMPUTERS; RECONFIGURABLE ARCHITECTURES; RECONFIGURABLE HARDWARE;

BIT STREAM; BITSTREAM GENERATION; CIRCUIT DESCRIPTION; DESIGN METHODOLOGY; FPGA PROGRAMMING; HIGH SPEED; RECONFIGURABLE COMPUTING SYSTEMS; SPEED IMPROVEMENT;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 84963984083     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (19)

1. Peter Bellows and Brad Hutchings. JHDL - An HDL for Reconfigurable Systems. FCCM'98. IEEE Computer Society. 1998.
2. Per Bjesse, Koen Claessen, Mary Sheeran and Satnam Singh. Lava: Hardware Design in Haskell. International Conference on Lisp and Functional Programming 98. Springer-Verlag. 1998.
3. M. Chu, N. Weaver, K. Sulimma, A. DeHon and J. Wawrzynek. Object Oriented Circuit-Generators in Java. IEEE Computer Society. 1998
4. Brad Hutchings, Peter Bellows, Joseph Hawkings, Scott Hemmert, Brent Nelson, Mike Rytting. A CAD Suite for High-Performance FPGA Design. FCCM'99. IEEE Computer Society. 1999.
5. IEEE Std. 1076-1987. IEEE Standard VHDL Reference Manual. 1987.
6. W. Luk and S. McKeever. Pebble: a language for parameterised and reconfigurable hardware design. Field-Programmable Logic and Applications. LNCS 1482. Springer-Verlag. 1998.
7. Satnam Singh. Architectural Descriptions for FPGA Circuits. FCCM'95. IEEE Computer Society. 1995.
8. M. Sheeran, G. Jones. Circuit Design in Ruby. Formal Methods for VLSI Design, J. Stanstrup, North Holland, 1992.
9. Xilinx. XC6200 FPGA Family Data Sheet. Xilinx Inc. 1995.
10. S. Guccione and D. Levi. XBI: A Java-based interface to FPGA hardware. Configurable Computing Technology and its uses in High Performance Computing, DSP and Systems Engineering. SPIE 1998.
11. S. McMillan, B. Blodget, and S. Guccione. VirtexDS: A Virtex Device Simulator. SPIE 2000.
12. S. McMillan and S. Guccione. Partial Run-Time Reconfiguration Using JRTR. Proceedings of the 10th International Workshop on Field-Programmable Logic and Applications, LNCS 1896, 2000.
13. E. Keller. JRoute: A Run-Time Routing API for FPGA Hardware. 7th Reconfigurable Architectures Workshop, Lecture Notes in Computer Science 1800, pp 874-881, Cancun, Mexico, May, 2000.
14. Nicholas McKay and Satnam Singh. Dynamic Specialisation of XC6200 FPGAs by Partial Evaluation. Field-Programmable Logic and Applications. Tallinn, Estonia. Springer-Verlag. 1998.
15. Schaps, G.L. Compiler Construction with ANTLR and Java. Dr. Dobb's. Journal, March 1999
16. R. Woods, S. Ludwig, J. Heron, D. Trainor, and S. Gehring. FPGA synthesis on the XC6200 using IRIS and Hades. FCCM'97. IEEE Computer Society. 1997.
17. Eric Lechner and Steven A. Guccione. The Java environment for reconfigurable computing. In W. Luk, P. Y. K. Cheung, and M. Glesner, editors, Springer-Verlag, Berlin, September 1997. FPL 1997. LNCS 1304.
18. Satnam Singh and Carl Johan Block. Formal Verification of Reconfigurable Cores. FCCM'99. IEEE Computer Society. 1999.
19. Satnam Singh. Death of the RLOC? FCCM'00. IEEE Computer Society. 2000.