Active GHz clock network using distributed PLLs

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2000, Pages 174-175

  Gutnik, V ^a   Chandrakasan, A ^a  

^a USA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITORS; CHIP SCALE PACKAGES; GAIN MEASUREMENT; GATES (TRANSISTOR); LOGIC GATES; MICROPROCESSOR CHIPS; MOS DEVICES; PHASE LOCKED LOOPS; PHASE SEQUENCE INDICATORS; PULSE GENERATORS; SPURIOUS SIGNAL NOISE; TIMING JITTER; VARIABLE FREQUENCY OSCILLATORS;

PHASE-FREQUENCY DETECTORS (PFD);

INTERCONNECTION NETWORKS;

EID: 0034429721     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. Clocking design and analysis for a 600 MHz alpha microprocessor
2. A 0.35m CMOS 3-880MHz PLL N/2 clock multiplier and distribution network with low jitter for microprocessors
3. An adaptive digital deskewing circuit for clock distribution networks
4. Distributed synchronous clocking