SDVMR: A Scalable Firmware for FPGA-based Multi-Core Systems-on-Chip

Lecture Notes in Informatics (LNI), Proceedings - Series of the Gesellschaft fur Informatik (GI)

Volumn P-124, Issue , 2008, Pages 49-58

  Hofmann, Andreas ^a   Waldschmidt, Klaus ^a  

^a GOETHE UNIVERSITY   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION PROGRAMS; BUDGET CONTROL; DATA HANDLING; EMBEDDED SYSTEMS; FIRMWARE; SYSTEM-ON-CHIP; VIRTUAL REALITY; VIRTUALIZATION;

DESIGN GOAL; EMBEDDED-SYSTEM; ENERGY BUDGETS; IMPLEMENTATION PLATFORMS; LIMITED ENERGIES; MULTI-CORE SYSTEMS; MULTI-CORES; PERFORMANCE; RUN-TIME RECONFIGURATION; SYSTEMS-ON-CHIP;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 85083902674     PISSN: 16175468     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

1. [HDHW06] Jan Haase, Markus Damm, Dennis Hauser, and Klaus Waldschmidt. Reliability-aware power management of Multi-Core Processors, 2006. DIPES 2006, Braga, Portugal.
2. [HEKW04] Jan Haase, Frank Eschmann, Bernd Klauer, and Klaus Waldschmidt. The SDVM: A Self Distributing Virtual Machine. In Organic and Pervasive Computing – ARCS 2004: International Conference on Architecture of Computing Systems, volume 2981 of Lecture Notes in Computer Science, Heidelberg, 2004. Springer Verlag.
3. [HEW05] Jan Haase, Frank Eschmann, and Klaus Waldschmidt. The SDVM - an Approach for Future Adaptive Computer Clusters. In 10th IEEE Workshop on Dependable Parallel, Distributed and Network-Centric Systems (DPDNS 05), Denver, Colorado, USA, April 2005.
4. +05] Gabriel Lipsa, Andreas Herkersdorf, Wolfgang Rosenstiel, Oliver Bringmann, and Walter Stechele. Towards a Framework and a Design Methodology for Autonomous SoC. In Uwe Brinkschulte, Jürgen Becker, Dietmar Fey, Christian Hochberger, Thomas Martinetz, Christian Müller-Schloer, Hartmut Schmeck, Theo Ungerer, and Rolf P. Würtz, editors, ARCS Workshops, pages 101–108. VDE Verlag, 2005.
5. [LMVV05] Roman L. Lysecky, Kris Miller, Frank Vahid, and Kees A. Vissers. Firm-core Virtual FPGA for Just-in-Time FPGA Compilation (abstract only). In Herman Schmit and Steven J. E. Wilton, editors, FPGA, page 271. ACM, 2005.
6. [LV04] Roman Lysecky and Frank Vahid. A Configurable Logic Architecture for Dynamic Hardware/Software Partitioning. In DATE’04: Proceedings of the conference on Design, automation and test in Europe, page 10480, Washington, DC, USA, 2004. IEEE Computer Society.
7. [LV05] Roman Lysecky and Frank Vahid. A Study of the Speedups and Competitiveness of FPGA Soft Processor Cores using Dynamic Hardware/Software Partitioning. In DATE’05: Proceedings of the conference on Design, Automation and Test in Europe, pages 18–23, Washington, DC, USA, 2005. IEEE Computer Society.
8. [LVT04] Roman Lysecky, Frank Vahid, and Sheldon X.-D. Tan. Dynamic FPGA routing for just-in-time FPGA compilation. In DAC’04: Proceedings of the 41st annual conference on Design automation, pages 954–959, New York, NY, USA, 2004. ACM Press.