IN PROCESS STRESS ANALYSIS OF FLIP CHIP ASSEMBLIES DURING UNDERFILL CURE

ASME International Mechanical Engineering Congress and Exposition, Proceedings (IMECE)

Volumn 1997-K, Issue , 1997, Pages 7-14

  Palaniappan, Prema ^a   Baldwin, Daniel F ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CHIP SCALE PACKAGES; DIES; FLIP CHIP DEVICES; GLASS TRANSITION; RESIDUAL STRESSES; STRESS ANALYSIS; THERMAL EXPANSION;

ELECTRONIC INDUSTRIES; FLIP CHIP; FLIP CHIP ASSEMBLIES; FLIP CHIP ON BOARDS; FLIP CHIP TECHNOLOGIES; IN-PROCESS; PERFORMANCE; STRESSES ANALYSIS; UNDERFILL MATERIALS; UNDERFILLS;

CURING;

EID: 85053876748     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1115/IMECE1997-1221     Document Type: Conference Paper

References (10)

1. Palaniappan, P. and Baldwin, D. F., 1997, “Preliminary In-Process Stress Analysis of Flip-Chip Assemblies During Underfill,” 30th International Symposium on Microelectronics, Philadelphia, PA, Oct.
2. Sweet, J. N., D. W. Peterson, M. R. Tuck, J. M. Green, 1993, “Assembly Test Chip Ver. 04(ATC04) Description and User Guide”, Sandia National Laboratories, SAND93-1901, August, pp. 2-27.
3. Sweet, J. N., D. W. Peterson, J. A. Emerson, S. N. Burchett, 1995, “Experimental Measurement and Finite Element Calculations for Liquid Encapsulated ATC04 Assembly Test Chips”, Proceedings 1995 ASME Int. Meeh. Engr. Congress, Applications of Experimental Mechanics to Electronic Packaging, Vol EPP-13, Nov 12-17.
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6. Koopman, N., G. Adema, S. Nangalia, 1995, “Flip-Chip Process Development Techniques using a Modified Laboratory Aligner Bonder”, lEMT, October.
7. Wang, D. W., K. I. Papathomas, 1993, “Encapsulant for Fatigue Life Enhancement of Controlled-Collapse Chip Connection (C4)”, IEEE Transactions on Components, Hybrids, and Manufacturing Technology, Vol. 16, pp. 863 - 867.
8. Machuga, S. C., S. E. Lindsey, K. D. Moore, A. F. Skipor, “Encapsulation of Flip Chip Structures”, 1992 lEEE/CHMT International Electronics Manufacturing Technology Symposium, pp. 53-58.
9. Bittie, D. A., Suhling, J.C., Beaty, R. E., Jaeger, R. C., and Johnson, R. W., 1991, “Piezoresistive Stress Sensors for Structural Analysis of Electronics Packages, Journal of Electronic Packaging, Vol. 113, p. 203.
10. Peterson, D. W., J. N. Sweet S. N. Burchett, 1997, “Validating Theoretical Calculations of Thermomechanical Stresses and Deformation using the ATC4.1 Flip-Chip Test Vehicle”, Sandia National Laboratories, to be presented Sept 7-11.