Schedulability Analysis of Non-preemptive Real-Time Scheduling for Multicore Processors with Shared Caches

Proceedings - Real-Time Systems Symposium

Volumn 2018-January, Issue , 2017, Pages 199-208

  Xiao, Jun ^a   Altmeyer, Sebastian ^a   Pimentel, Andy ^a  

^a UNIVERSITY OF AMSTERDAM   (Netherlands)

Author keywords

Multi Core Systems; Scheduling; Shared Caches

Indexed keywords

EMBEDDED SYSTEMS; INTERACTIVE COMPUTER SYSTEMS; ITERATIVE METHODS; REAL TIME SYSTEMS; SCHEDULING;

INTEGER PROGRAMMING FORMULATIONS; MULTI-CORE PROCESSOR; MULTI-CORE SYSTEMS; NON-PREEMPTIVE; REAL TIME SCHEDULING; SCHEDULABILITY; SCHEDULABILITY ANALYSIS; SCHEDULING; SHARED CACHE; UPPER BOUND;

INTEGER PROGRAMMING;

EID: 85046338278     PISSN: 10528725     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/RTSS.2017.00026     Document Type: Conference Paper

References (23)

1. S. Altmeyer, R. I. Davis, L. Indrusiak, C. Maiza, V. Nelis, and J. Reineke. A generic and compositional framework for multicore response time analysis. In 23rd RTNS, pages 129-138. ACM, 2015.
2. T. P. Baker. Multiprocessor edf and deadline monotonic schedulability analysis. In 24th IEEE RTSS, 2003, pages 120-129, Dec 2003.
3. S. Baruah. Techniques for multiprocessor global schedulability analysis. In 28th IEEE International RTSS, RTSS '07, pages 119-128, Washington, DC, USA, 2007. IEEE Computer Society.
4. E. Berg, H. Zeffer, and E. Hagersten. A statistical multiprocessor cache model. In 2006 IEEE ISPASS, pages 89-99, March 2006.
5. M. Bertogna, M. Cirinei, and G. Lipari. Schedulability analysis of global scheduling algorithms on multiprocessor platforms. IEEE Transactions on Parallel and Distributed Systems, 20(4):553-566, April 2009.
6. M. Caccamo, M. Cesati, R. Pellizzoni, E. Betti, R. Dudko, and R. Mancuso. Real-time cache management framework for multi-core architectures. In 2013 IEEE 19th RTAS, RTAS '13, pages 45-54, Washington, DC, USA, 2013. IEEE Computer Society.
7. K. L. Clarkson. Las vegas algorithms for linear and integer programming when the dimension is small. J. ACM, 42:488-499, 1995.
8. G. Gracioli and A. A. Fröhlich. An experimental evaluation of the cache partitioning impact on multicore real-time schedulers. In 2013 IEEE 19th International Conference on Embedded and Real-Time Computing Systems and Applications, pages 72-81, Aug 2013.
9. N. Guan, M. Stigge, W. Yi, and G. Yu. Cache-Aware scheduling and analysis for multicores. In 7th ACM international conference on Embedded software, pages 245-254. ACM, 2009.
10. N. Guan, W. Yi, Q. Deng, Z. Gu, and G. Yu. Schedulability analysis for non-preemptive fixed-priority multiprocessor scheduling. Journal of Systems Architecture, 57(5):536-546, 2011.
11. D. Hardy, T. Piquet, and I. Puaut. Using bypass to tighten wcet estimates for multi-core processors with shared instruction caches. In 2009 30th IEEE RTSS, pages 68-77, Dec 2009.
12. D. Hardy and I. Puaut. Wcet analysis of multi-level non-inclusive set-Associative instruction caches. In 2008 RTSS, pages 456-466, Nov 2008.
13. H. Kim, A. Kandhalu, and R. Rajkumar. A coordinated approach for practical os-level cache management in multi-core real-time systems. In 2013 25th ECRTS, pages 80-89, July 2013.
14. J. Lee, K. G. Shin, I. Shin, and A. Easwaran. Composition of schedulability analyses for real-time multiprocessor systems. IEEE Transactions on Computers, 64(4):941-954, April 2015.
15. Y. Liang, H. Ding, T. Mitra, A. Roychoudhury, Y. Li, and V. Suhendra. Timing analysis of concurrent programs running on shared cache multicores. Real-Time Systems, 48(6):638-680, 2012.
16. J. Liedtke, H. Hartig, and M. Hohmuth. Os-controlled cache predictability for real-time systems. In Proceedings Third IEEE Real-Time Technology and Applications Symposium, pages 213-224, Jun 1997.
17. M. Shekhar, A. Sarkar, H. Ramaprasad, and F. Mueller. Semi-partitioned hard-real-time scheduling under locked cache migration in multicore systems. In 2012 24th ECRTS, ECRTS '12, pages 331-340, Washington, DC, USA, 2012. IEEE Computer Society.
18. R. Stafford. Random vectors with fixed sum http://www.mathworks.com/matlabcentral/fileexchange/9700, 2006.
19. V. Suhendra and T. Mitra. Exploring locking & partitioning for predictable shared caches on multi-cores. In 2008 45th ACM/IEEE DAC, pages 300-303, June 2008.
20. B. C. Ward, J. L. Herman, C. J. Kenna, and J. H. Anderson. Making shared caches more predictable on multicore platforms. In 2013 25th ECRTS, pages 157-167, July 2013.
21. R. Wilhelm, J. Engblom, A. Ermedahl, N. Holsti, S. Thesing, D. Whalley, G. Bernat, C. Ferdinand, R. Heckmann, T. Mitra, F. Mueller, I. Puaut, P. Puschner, J. Staschulat, and P. Stenström. The worst-case executiontime problem-overview of methods and survey of tools. ACM Trans. Embed. Comput. Syst., 7(3):36:1-36:53, May 2008.
22. M. Xu, L. T. X. Phan, H. Y. Choi, and I. Lee. Analysis and implementation of global preemptive fixed-priority scheduling with dynamic cache allocation. In 2016 IEEE RTAS, pages 1-12, April 2016.
23. W. Zhang and J. Yan. Accurately estimating worst-case execution time for multi-core processors with shared direct-mapped instruction caches. In 2009 15th IEEE International Conference on RTCSA, pages 455-463, Aug 2009.