Evolvable hardware or learning hardware? induction of state machines from temporal logic constraints

Proceedings of the 1st NASA/DoD Workshop on Evolvable Hardware

Volumn , Issue , 1999, Pages 129-138

  Perkowski, M ^a   Chebotarev, A ^b   Mishchenko, A ^a  

^a PORTLAND STATE UNIVERSITY   (United States)

^b V M GLUSHKOV INSTITUTE OF CYBERNETICS   (Ukraine)

Author keywords

[No Author keywords available]

Indexed keywords

FIELD PROGRAMMABLE GATE ARRAYS (FPGA); FUNCTIONAL PROGRAMMING; HARDWARE; LEARNING ALGORITHMS; MANY VALUED LOGICS; MAPPING; NASA; TEMPORAL LOGIC;

BINARY SWITCH; DETERMINIZATION; EVOLVABLE HARDWARE; FUNCTIONAL DECOMPOSITION; LEARNING STRATEGY; LOGIC CONSTRAINTS; LOGIC FUNCTIONS; STRUCTURAL MAPPING;

COMPUTER CIRCUITS;

EID: 85031541514     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EH.1999.785444     Document Type: Conference Paper

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