Layout-driven synthesis for submicron technology: Mapping expansions to regular lattices

International Symposium on IC Technology, Systems and Applications

Volumn 7, Issue , 1997, Pages 668-671

  Perkowski, Marek A ^a   Pierzchala, Edmund ^a   Drechsler, Rolf ^b  

^a PORTLAND STATE UNIVERSITY   (United States)

^b UNIVERSITY OF FREIBURG   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATIONAL GEOMETRY; ELECTRIC NETWORK SYNTHESIS; FIELD PROGRAMMABLE GATE ARRAYS; MANY VALUED LOGICS; TREES (MATHEMATICS); VLSI CIRCUITS;

MAPPING EXPANSIONS; REGULAR LATTICES; SHANNON EXPANSION; SUBMICRON TECHNOLOGY;

INTEGRATED CIRCUIT LAYOUT;

EID: 1842728675     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (21)

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