High flexibility CMOS SRAM generator using multiplan architecture

Proceedings - 12th Annual IEEE International ASIC/SOC Conference

Volumn , Issue , 1999, Pages 414-417

  Clerc, Sylvain ^a   Dufourt, Denis ^a   Zangara, Louis ^a  

^a Dolphin Integralion SA   (France)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; CMOS INTEGRATED CIRCUITS; MEMORY ARCHITECTURE; STATIC RANDOM ACCESS STORAGE;

CMOS PROCESSS; FORM FACTORS; HIGH FLEXIBILITY; MEMORY ARRAY; MEMORY CONFIGURATION; MEMORY OPERATIONS; MERIT FACTOR; SRAM GENERATOR;

INTEGRATED CIRCUIT DESIGN;

EID: 85025389209     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASIC.1999.806546     Document Type: Conference Paper

References (3)

1. A. K. Sharma, Semiconductor Memorie. IEEE Press 1097. p. 16.
2. K. W, Mai et al, "Low Power SRAM Design Using Half-Swing Pulse-Mode Techniques", IEEE J. Solid-State Circuits, vol. 33, pp 1659-1671, Nov J998.
3. B. S, Amrutur M. A, Horowitz, "A Replica Technique for Wordline and Sense Control in Low-Power SRAM's", IEEE J. Solid-State Circuits, vol. 33, pp 1208-1219, Aug 1998.