1.2 V full-swing BiDPL logic gate

Microelectronics Journal

Volumn 29, Issue 7, 1998, Pages 421-429

  Margala, Martin ^a   Durdle, Nelson G ^a  

^a UNIVERSITY OF ALBERTA   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

BIPOLAR TRANSISTORS; CAPACITANCE; CMOS INTEGRATED CIRCUITS; ENERGY EFFICIENCY; ENERGY UTILIZATION; INTEGRATED CIRCUIT TESTING; MOS DEVICES; OPTIMIZATION;

DOUBLE PASS TRANSISTOR LOGIC; LOW POWER METHODOLOGY;

LOGIC GATES;

EID: 0032119164     PISSN: 00262692     EISSN: None     Source Type: Journal    
DOI: 10.1016/s0026-2692(97)00082-7     Document Type: Article

References (7)

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3. Y.K. Seng, S.S. Rofail, 1.1 V high speed, low power BiCMOS logic circuit, Electron. Lett. 31 (13) (1995) 1039-1041.
4. M. Suzuki, N. Ohkubo, T. Shinbo, T. Yamanaka, A. Shimizu, K. Sasaki, Y. Nakagome, A 1.7-ns 32-b CMOS ALU in double pass-transistor logic, IEEE Journal of Solid-State Circuits 28 (11) (1993) 1145-1151.
5. J.M. Rabaey and M. Pedram (eds), Low Power Design Methodologies, Kluwer Academic, Boston, 1996, 367 pp.
6. J.M. Rabaey, Digital Integrated Circuits, Prentice Hall, Englewood Cliffs, 1996, 702 pp.
7. P.A. Raje, K.C. Saraswat, K.M. Cham, A new methodology for design of BiCMOS gates and comparison with CMOS, IEEE Trans. Electron Devices 39 (2) (1992) 339-347.