Novel low-voltage low-power full-swing BiNMOS logic gate

International Journal of Electronics

Volumn 84, Issue 5, 1998, Pages 487-498

  Margala, Martin ^a   Durdle, Nelson G ^a  

^a UNIVERSITY OF ALBERTA   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 0344000306     PISSN: 00207217     EISSN: 13623060     Source Type: Journal    
DOI: 10.1080/002072198134599     Document Type: Article

References (9)

1. Bellaouar, A., Elmasry, M. I., and Embabi, S. H. K., 1995, Bootstrapped full-swing BiCMOS/BiNMOS logic circuits for 1.2—3.3 V supply voltage regime. IEEE Journal of Solid-state Circuits, 30, 629-636.
2. Embabi, S. H. K., Bellaouar, A., and Elmasry, M. I., 1993, Digital BiCMOS Integrated Circuit Design (Boston, MA: Kluwer Academic).
3. 2CMOS) gate for low-voltage applications. IEEE Journal of Solid-state Circuits, 30, 47-53.
4. Rabaey, J. M., 1966, Digital Integrated Circuits (Englewood Cliffs, NJ: Prentice-Hall).
5. Rabaey, J. M., and Pedram, M., (eds), 1996, Low Power Design Methodologies (Boston, MA: Kluwer Academic).
6. Raje, P. A., Saraswat, K. C., and Cham, K. M., 1992, A new methodology for design of BiCMOS gates and comparison with CMOS. IEEE Transactions on Electron Devices, 39, 339-347.
7. Seng, Y. K., and Rofail, S. S., 1995, 1.1V high speed, low power BiCMOS logic circuit. Electronics Letters, 31, 1039-1041.
8. Seng, Y. K., and Rofail, S. S., 1996, 1.1 V full-swing double sbootstrapped BiCMOS logic gates. IEE Proceedings—Circuits, Devices and Systems, 143, 41-45.
9. Suzuki, M., Ohkubo, N., Shinbo, T, Yamanaka, T, Shimizu, A., Sasaki, K., and Nakagome, Y., 1993, A 1.5-ns 32-b CMOS ALU in double pass-transistor logic. IEEE Journal of Solid-state Circuits, 28, 1145-1151.