Implementing decay techniques using 4t quasi-static memory cells

IEEE Computer Architecture Letters

Volumn 1, Issue 1, 2002, Pages 10-

  Juangt, Philo ^a   Diodato*, Phil ^b   Kaxirast, Stefanos ^b   Skadron*, Kevin ^c  

^a PRINCETON UNIVERSITY   (United States)

^b AGERE SYSTEMS   (United States)

^c UNIVERSITY OF VIRGINIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 85008026157     PISSN: 15566056     EISSN: None     Source Type: Journal    
DOI: 10.1109/L-CA.2002.5     Document Type: Article

References (19)

1. D. Brooks, V. Tiwari, and M. Martonosi. Wattch: A Framework for Architecture-Level Power Analysis and Optimizations. In ISCA27, June 2000.
2. D. Burger, T. M. Austin, and S. Bennett. Evaluating Future Microprocessors: the SimpleScalar Tool Set. Tech. Report TR-1308, Univ. of Wisconsin-Madison Computer Sciences Dept., July 1996.
3. J. Cortadella and T. Jove. Dynamic RAM for On-chip Instruction Caches. Computer Architecture News, 16(4):45-50, Sept. 1988.
4. K. Diefendorff. Pentium III = Pentium II + SSE. Microprocessor Report. Mar. 8 1999.
5. P. Diodato et al. Merged DRAM-LOGIC in the Year 2001. Proc. of the IEEE International Workshop on Memory, Technology, Design, and Testing. Aug_ 1998.
6. P. Diodato et al. Embedded DRAM: An Element and Circuit Evaluation. In IEEE Custom Integrated Circuits Conference, Jun 2001.
7. K. Flautner et al. Drowsy Caches: Simple Techniques for Reducing Leakage Power. In ISCA29, May 2002.
8. S. Hanamura et al. A 256K CMOS SRAM with Internal Refresh. In ISSCC. 1987.
9. S. Heo et al. Dynamic Fine-Grain Leakage Reduction using Leakage-Biased Bitlines. In ISCA29, May 2002.
10. Z. Hu et al. Applying Decay Strategies to Branch Predictors for Leakage Energy Savings. In ICCD, Sep. 2002.
11. Z. Hu et al. Managing Leakage for Transient Data : Decay and Quasi-Static 4T Memory Cells. In ISLPED, Aug. 2002.
12. S. Kaxiras, Z. Hu, and M. Martonosi. Cache Decay: Exploiting Generational Behavior to Reduce Cache Leakage Power. In ISCA28, July 2001.
13. D. Lee and R. Katz. Using Cache Mechanism to Exploit Non-refreshing DRAM's for On-Chip Memories. IEEE Journal of Solid-State Circuits, 26(4):657-661, Apr. 1991.
14. R. Lyons et al. CMOS Static Memory With a New Four-Transistor Memory Cell. Proc. of the 1987 Stanford Conf. On Advanced Re-search in VLSI, pages 111–132.
15. S. Schuster, L. Terman, and R. Franch. A 4-Device CMOS Static RAM Cell Using Sub-Threshold Conduction. In Symposium on VLSI Technology, Systems, and Applications, 1987.
16. The Standard Performance Evaluation Corporation. WWW Site. http://www.spec.org, Dec. 2000.
17. A. G. Varadi. Quasi-Static MOS Memory Array with Standby Operation. US Patent Number 4,120,047.
18. W. Wolf. Modern VLSI Design: Systems on Silicon. Prentice Hall, 1998. Prentice-Hall.
19. S.-H. Yang et al. An Integrated Circuit/Architecture Approach to Reducing Leakage in Deep-Submicron High-Performance I-Caches. In HPCA7, Jan. 2001.