Effects of online fault detection mechanisms on Probabilistic Timing Analysis

2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2016

Volumn , Issue , 2016, Pages 41-46

  Chen, Chao ^a   Panerati, Jacopo ^a   Beltrame, Giovanni ^a  

^a ÉCOLE POLYTECHNIQUE DE MONTRÉAL   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

CACHE MEMORY; DEFECTS; FAULT TOLERANCE; HIDDEN MARKOV MODELS; INTERACTIVE COMPUTER SYSTEMS; MARKOV PROCESSES; NANOTECHNOLOGY; REAL TIME SYSTEMS; TIMING CIRCUITS; VLSI CIRCUITS;

DETECTION MECHANISM; DETERMINISTIC SYSTEMS; DIFFERENT MECHANISMS; ON-LINE FAULT DETECTION; RULE BASED DETECTION; SOFTWARE TIMING ANALYSIS; TRANSIENT AND PERMANENT FAULT; WORST-CASE EXECUTION TIME;

FAULT DETECTION;

EID: 84999133338     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DFT.2016.7684067     Document Type: Conference Paper

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