Design space exploration of FPGA-based Deep Convolutional Neural Networks

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn 25-28-January-2016, Issue , 2016, Pages 575-580

  Motamedi, Mohammad ^a   Gysel, Philipp ^a   Akella, Venkatesh ^a   Ghiasi, Soheil ^a  

^a University of California   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ACCELERATION; COMPLEX NETWORKS; COMPUTER AIDED DESIGN; CONVOLUTION; ENERGY EFFICIENCY; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); IMAGE CLASSIFICATION; NEURAL NETWORKS; PATTERN RECOGNITION; SPEECH RECOGNITION;

ACCELERATOR ARCHITECTURES; CONVOLUTIONAL NEURAL NETWORK; CUSTOM HARDWARES; DESIGN SPACE EXPLORATION; FPGA DEVICES; PERFORMANCE ESTIMATION; STATE OF THE ART;

INTEGRATED CIRCUIT DESIGN;

EID: 84996606606     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2016.7428073     Document Type: Conference Paper

References (10)

1. S. Cadambi, A. Majumdar, M. Becchi, S. Chakradhar, H. P. Graf. A programmable parallel accelerator for learning and classification. In Proceedings of the 19th international conference on Parallel architectures and compilation techniques, pages 273-284. ACM, 2010.
2. S. Chakradhar, M. Sankaradas, V. Jakkula, S. Cadambi. A dynamically configurable coprocessor for con-olutional neural networks. In Proceedings of the 37th Annual International Symposium on Computer Architecture, ISCA '10, pages 247-257, New York, NY, USA, 2010. ACM.
3. Y. Chen, T. Luo, S. Liu, S. Zhang, L. He, J. Wang, L. Li, T. Chen, Z. Xu, N. Sun, et al. Dadiannao: A machine-learning supercomputer. In Microarchitecture (MICRO), 2014 47th Annual IEEE/ACM International Symposium on, pages 609-622. IEEE, 2014.
4. J. Cong and B. Xiao. Minimizing computation in con-olutional neural networks. In Artificial Neural Networks and Machine Learning-ICANN 2014, pages 281-290. Springer, 2014.
5. C. Farabet, B. Martini, B. Corda, P. Akselrod, E. Culurciello, Y. LeCun. Neuflow: A runtime reconfigurable dataflow processor for-ision. In Computer-ision and Pattern Recognition Workshops (C-PRW), 2011 IEEE Computer Society Conference on, pages 109-116. IEEE, 2011.
6. C. Farabet, C. Poulet, J. Y. Han, Y. LeCun. Cnp: An fpga-based processor for con-olutional networks. In Field Programmable Logic and Applications, 2009. FPL 2009. International Conference on, pages 32-37. IEEE, 2009.
7. A. Krizhe-sky, I. Sutske-er, G. E. Hinton. Imagenet classification with deep con-olutional neural networks. In Ad-ances in neural information processing systems, pages 1097-1105, 2012.
8. M. Peemen, A. A. Setio, B. Mesman, H. Corporaal. Memory-centric accelerator design for con-olutional neural networks. In Computer Design (ICCD), 2013 IEEE 31st International Conference on, pages 13-19. IEEE, 2013.
9. M. Sankaradas,-. Jakkula, S. Cadambi, S. Chakradhar, I. Durdano-ic, E. Cosatto, H. P. Graf. A massi-ely parallel coprocessor for con-olutional neural networks. In Applicationspecific Systems, Architectures and Processors, 2009. ASAP 2009. 20th IEEE International Conference on, pages 53-60. IEEE, 2009.
10. C. Zhang, P. Li, G. Sun, Y. Guan, B. Xiao, J. Cong. Optimizing fpga-based accelerator design for deep con-olutional neural networks. In Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, pages 161-170. ACM, 2015.