Annealing of ultra-shallow implanted junctions using arc-lamp technology: Achieving the 90 nm node

9th International Conference on Advanced Thermal Processing of Semiconductors, RTP 2001

Volumn , Issue , 2001, Pages 87-93

  Tichy, R S ^a   Elliott, K ^b   McCoy, S ^b   Sing, D C ^a  

^a SEMATECH   (United States)

^b Vortek Industries Ltd   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

ARC LAMPS; GERMANIUM; HEAT TREATMENT; NANOTECHNOLOGY;

ANNEAL TEMPERATURES; DOPANT DIFFUSION; IMPLANTED JUNCTIONS; LOW ENERGY IMPLANTS; PEAK TEMPERATURES; PRE-AMORPHIZATION; SOURCE/DRAIN EXTENSION; SOURCE/DRAIN JUNCTIONS;

SEMICONDUCTOR JUNCTIONS;

EID: 84982318674     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/RTP.2001.1013749     Document Type: Conference Paper

References (6)

1. International Technology Roadmap for Semiconductrs - Front End Processes, Semiconductor Industry Association, p. 124, 1999
2. A. Agarwal, H-J Gossman, and A.T. Fiory, Mat. Res. Soc. Symp. Proc., vol. 568 (1999) p. 19
3. E.J.H Collart et al., Proceeding of the USJ Conf., p. 48, 1997
4. A. Jain, Proc. of the Elec. Chem. Soc. 2000
5. A.T. Fiory, and K.K. Bourdelle, Appl. Phys. Let., vol. 74 (1999), p. 2658
6. K.S. Jones and G.A. Rozgonyi, "Extended Defects from Ion Implantation and Annealing," in Rapid Thermal Processing, R.B. Fair Ed., Academic Press Inc. 1993