On the VLSI area and bisection width of star graphs and hierarchical cubic networks

Proceedings - 15th International Parallel and Distributed Processing Symposium, IPDPS 2001

Volumn , Issue , 2001, Pages

  Yeh, Chi Hsing ^a   Parhami, B ^b  

^a QUEEN S UNIVERSITY   (Canada)

^b University of California   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

GEOMETRY; HYPERCUBE NETWORKS; INTEGRATED CIRCUIT LAYOUT; VLSI CIRCUITS;

BISECTION WIDTH; GRID MODEL; HYPERCUBE; MULTILAYER LAYOUTS; OPTIMAL LAYOUT; STAR GRAPHS; THOMPSON; VLSI LAYOUT;

GRAPH THEORY;

EID: 84981267021     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IPDPS.2001.925019     Document Type: Conference Paper

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