Comparison of 32-bit multipliers for various performance measures

Proceedings of the International Conference on Microelectronics, ICM

Volumn 2000-October, Issue , 2000, Pages 75-80

  Shah, S ^a   Al Khalili, A J ^a   Al Khalili, D ^a  

^a Gina Cody School of Engineering and Computer Science   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

MICROELECTRONICS;

ARRAY MULTIPLIERS; MULTIPLIER ARCHITECTURE; PERFORMANCE MEASURE; RADIX-4; SERIAL PARALLELS; TWIN PIPES; WALLACE TREE;

FORESTRY;

EID: 84979587865     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICM.2000.916418     Document Type: Conference Paper

References (9)

1. Shailesh Shah, "Design and Comparison of 32-bit Multipliers for Various Performance Measures", MEng. Project Report, Concordia University, January 2000.
2. O. Salomon, J.-M. Green, and H. Klar, "General Algorithms for a Simplified Addition of 2's Complement Numbers", IEEE Journal of Solid-State Circuits, Vol.30, No.7, pp.839-844, July 1995.
3. A.D.Booth, "A signed binary multiplication technique", Quart. J. Math., vol. IV, pt. 2, 1951
4. C.S.Wallace, "A suggestion for a fast multiplier", IEEE Trans. Electron. Comp., vol. EC-13, pp. 14-17, Feb. 1964.
5. V.G Oklobdzija, "A Method for Speed Optimized Partial Product Reduction and Generation of Fast Parallel Multipliers Using an Algorithmic Approach", IEEE Transactions on Computers, Vol. 45, No, 3, pp.294-305, March 1996.
6. Jalil Fadavi-Ardekani, "M x N Booth Encoded Multiplier Generator Using Optimized Wallace Trees", IEEE Transactions on VLSI Systems, Vol.1, No.2, pp. 120-125, June 1993.
7. P.Larsson-Edefors, "A 965-Mb/s 1.0um Standard CMOS Twin-Pipe Serial/Parallel Multiplier", IEEE Journal of Solid-State Circuits, Vol.31, No.2, pp.230-239, Feb.1995.
8. th Symposium On Computer Arithmetic, pp. 566-570, 1995.
9. th Symposium On Computer Arithmetic, pp. 186-195, 1997.