Design and implementation of low-power digit-serial multipliers

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 1997, Pages 186-195

  Chang, Yun Nan ^a   Satyanarayana, Janardhan H ^a   Parhi, Keshab ^a  

^a UNIVERSITY OF MINNESOTA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; DIGITAL SIGNAL PROCESSING; ELECTRIC POWER SUPPLIES TO APPARATUS; INTEGRATED CIRCUIT LAYOUT; PIPELINE PROCESSING SYSTEMS;

DIGIT SERIAL MULTIPLIERS; MODIFIED BOOTH RECORDING;

MULTIPLYING CIRCUITS;

EID: 0031373489     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (19)