Composable, parameterizable templates for high-level synthesis

Proceedings of the 2016 Design, Automation and Test in Europe Conference and Exhibition, DATE 2016

Volumn , Issue , 2016, Pages 744-749

  Matai, Janarbek ^a   Lee, Dajung ^a   Althoff, Alric ^a   Kastner, Ryan ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER PROGRAMMING; TECHNOLOGY TRANSFER;

COMMON DATUM; COMPOSABLE; FPGA PROGRAMMING; HARDWARE ARCHITECTURE; HARDWARE DESIGN; HARDWARE DESIGNERS; HARDWARE IMPLEMENTATIONS; PROGRAMMING ABSTRACTIONS;

HIGH LEVEL SYNTHESIS;

EID: 84973622028     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.3850/9783981537079_0821     Document Type: Conference Paper

References (23)

1. Vivado design suite user guide: High-level synthesis.
2. K. Asanovic et al. The landscape of parallel computing research: A view from berkeley. Technical report, Technical Report UCB/EECS-2006-183, EECS Department, University of California, Berkeley, 2006.
3. J. Bachrach et al. Chisel: constructing hardware in a scala embedded language. In Design Automation Conference, pages 1216-1225. ACM, 2012.
4. L. Carloni et al. Platform-based design for embedded systems. The Embedded Systems Handbook, pages 1-26, 2005.
5. C. Chen. Polyhedra scanning revisited. In ACM SIGPLAN Notices, volume 47, pages 499-508. ACM, 2012.
6. J. Cong et al. Charm: a composable heterogeneous accelerator-rich microprocessor. In ISLPED, pages 379-384. ACM, 2012.
7. D. L. Dill. Trace theory for automatic hierarchical verification of speed-independent circuits. 1988.
8. C. Gentsos et al. Real-time canny edge detection parallel implementation for fpgas. In ICECS, pages 499-502. IEEE, 2010.
9. N. George et al. Hardware system synthsis from domain-specific languages. In International Conference on Field Programmable Logic and Applications, 2014.
10. D. Guglielmo et al. A design methodology for compositional high-level synthesis of communication-centric socs. In Proceedings of the The 51st Annual Design Automation Conference on Design Automation Conference, pages 1-6. ACM, 2014.
11. R. J. Halstead et al. Compiling irregular applciations for reconfigurable systems. International Jounal on High Performance Computing and Networking, 2014.
12. W. He et al. An improved canny edge detector and its realization on fpga. In World Congress on Intelligent Control and Automation, pages 6561-6564. IEEE, 2008.
13. A. Irturk et al. A top-to-bottom design methodology for automatic generation of application specific architectures. TCAD, 30(8):1173-1183, 2011.
14. M. Karkooti et al. Fpga implementation of matrix inversion using qrd-rls algorithm. In Conference on Signals, Systems and Computers, pages 1625-1629, 2005.
15. J. Matai et al. Energy efficient canonical huffman encoding. In ASAP. IEEE, 2014.
16. D. A. Mathaikutty. Metamodeling driven IP reuse for system-on-chip integration and microprocessor design. PhD thesis, 2007.
17. A. Mazurkiewicz. Introduction to trace theory. The Book of Traces, 1995.
18. A. Papakonstantinou et al. Fcuda: Enabling efficient compilation of cuda kernels onto fpgas. In Application Specific Processors, pages 35-42. IEEE, 2009.
19. M. I. Shamos et al. Closest-point problems. In Symposium on Foundations of Computer Science. IEEE, 1975.
20. H. Tabkhi et al. Function-level processor (flp): Raising efficiency by operating at function granularity for market-oriented mpsoc. In ASAP. IEEE, 2014.
21. P. Zhang et al. Cmost: a system-level fpga compilation framework. In DAC. ACM, 2015.
22. Z. Zhang et al. Challenges and opportunities of esl design automation.
23. W. Zuo et al. Improving high level synthesis optimization opportunity through polyhedral transformations. In FPGA, pages 9-18. ACM, 2013.