Design of a JTAG based run time reconfigurable system

IEEE Symposium on FPGAs for Custom Computing Machines, Proceedings

Volumn , Issue , 1999, Pages 268-269

  Cousineau, Cynthia ^a   Laperle, François ^b   Savaria, Yvon ^a,b  

^a ÉCOLE POLYTECHNIQUE DE MONTRÉAL   (Canada)

^b MiroTech MicroSystems Inc   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER HARDWARE; FIELD PROGRAMMABLE GATE ARRAYS; LOGIC DESIGN; REDUCED INSTRUCTION SET COMPUTING; STATIC RANDOM ACCESS STORAGE; VIRTUAL REALITY;

CUSTOM COMPUTING MACHINES; HARDWARE MODULE FUNCTIONALITY; RUN TIME RECONFIGURABLE SYSTEM; VIRTUAL PROCESSING ELEMENTS;

TIME SHARING SYSTEMS;

EID: 0033488534     PISSN: 10823409     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. http://www.mirotech.com/product/x-c436.htm
2. IEEE Computer Society. IEEE Standard Test Access Port and Boundary-Scan Architecture. IEEE Std 1149.1-1990, May 1990.
3. Texas Instruments. TMS320C4x User's Guide, 1996.
4. Xilinx. The Programmable Logic, Data Book, July 1998.
5. Toshiba Corporation. TC5117405BSJ/BST-60/70 Data Sheet. DR16070295.
6. Texas Instruments. SN54LVT8980, SNLVT8980 Data Sheet, Embedded Test-Bus Controllers, 1997