VLSI design and implementation of high-speed Viterbi decoder

2002 International Conference on Communications, Circuits and Systems and West Sino Exposition, ICCCAS 2002 - Proceedings

Volumn , Issue , 2002, Pages 64-68

  You, Yu Xin ^a   Wang, Jin Xiang ^a   Lai, Feng Chang ^a   Ye, Yi Zheng ^a  

^a HARBIN INSTITUTE OF TECHNOLOGY   (China)

Author keywords

Decoder; T algorithm; Trace back; Viterbi

Indexed keywords

INTEGRATED CIRCUIT DESIGN; VITERBI ALGORITHM; VLSI CIRCUITS;

ADD-COMPARE-SELECT UNITS; DECODER; LOW-POWER DISSIPATION; PARALLEL COMPUTATION; SURVIVOR MEMORY UNITS; T-ALGORITHM; TRACE BACKS; VITERBI;

DECODING;

EID: 84969715346     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCCAS.2002.1180573     Document Type: Conference Paper

References (10)

1. K. Seki, S. Kubota, M. Mizoguchi and S. Kato, "Very low power consumption Viterbi decoder LSIC employing the SST (scarce state transition) scheme for multimedia mobile communications", Electronics-Letters, IEE, Vol.30, No.8, pp. 637-639, 1994.
2. Shuiji Kubota et al., "Novel Viterbi decoder VLSI implementation and its performance". IEEE Trans. on Communications, Vol.41, pp.1170-1178, 1993.
3. Ming-Hwa Chan et al., "IC design of an adaptive Viterbi Decoder", IEEE Trans. on Consumer Electronics, Vol.42, pp.52-61,1996.
4. G. C. Clark and J. B. Cain, Error Correction Coding for Digital Communications. New York: Plenum, 1981.
5. T. K. Truong, Ming-Tang Shih, Irving, S. Reed and E. H. Satorius, "A VLSI design for a Trace-back Viterbi decoder", IEEE transactions on Communications, Vol. 40, No.3, pp.616-624, 1992.
6. I. J. Fair and J. M. Brown, "Metric-based node synchronization of the Viterbi decoder in Satellite applications", International journal of satellite communications. Vol.18, pp.1-15, 2000.
7. th International Conference on VLSI Design, Goa, India, pp.611-614, Jan.7-10, 1999.
8. L.H.Charless Lee, Convolutional Coding: Fundamentals and Applications. Artech House, Inc., Boston-London, 1997.
9. Byonghyo Shim et al., "Pipelined VLSI architecture of the Viterbi decoder for IMT-200" in Global Telecommunications Conference, Rio de Janeiro, Brazil, pp.158-162, Dec., 1999.
10. Kai He and Gert Cauwenberghs, "Integrated 64-state parallel analog Viterbi decoder" in Proceedings of the 2000 IEEE International Symposium on Circuits and Systems, Genveva, Switzerland, pp.4:761-765, May 28-31, 2000.