Pipelined VLSI architecture of the Viterbi decoder for IMT-2000

Conference Record / IEEE Global Telecommunications Conference

Volumn 1, Issue , 1999, Pages

  Shim, Byonghyo ^a   Suh, Jung Chul ^a  

^a SoftDSP Corp   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER SIMULATION; CONGESTION CONTROL (COMMUNICATION); DATA STRUCTURES; DECODING; PIPELINE PROCESSING SYSTEMS; SIGNAL DETECTION; STORAGE ALLOCATION (COMPUTER); TELECOMMUNICATION TRAFFIC; VLSI CIRCUITS;

TRACEBACK ALGORITHMS; VITERBI DECODERS;

VOICE/DATA COMMUNICATION SYSTEMS;

EID: 0033293305     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)