Integrating symbolic techniques in ATPG-based sequential logic optimization

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 1999, Pages 516-520

  San Millan, Enrique ^a   Entrena, Luis ^a   Espejo, Jose A ^a   Chiusano, Silvia ^b   Corno, Fulvio ^b  

^a UNIVERSIDAD CARLOS III DE MADRID   (Spain)

^b POLITECNICO DI TORINO   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED APPROACH; LOGIC OPTIMIZATION; OPTIMIZATION APPROACH; REMOVAL ALGORITHMS; SEQUENTIAL LOGIC OPTIMIZATION; SYMBOLIC TECHNIQUES;

ALGORITHMS; AUTOMATIC TEST PATTERN GENERATION; EXHIBITIONS; INTEGRATED CONTROL;

OPTIMIZATION;

EID: 0006962126     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.1999.761175     Document Type: Conference Paper

References (14)

1. P. Ashar, S. Devadas, A. R. Newton. Sequential Logic Synthesis. Kluwer Academic Publishers, 1992
2. S. Malik, E. M. Sentovich, R. Brayton, A. Sangiovanni-Vincentelli. Retiming and Resynthesis: Optimizing Sequential Circuits Using Combinational Techniques. IEEE Transactions on CAD of Integrated Circuits and Systems, vol. 10, p. 74-84. January 1991
3. K.T. Cheng, On removing redundancy in sequential circuits, in Proc. 28th Design Automation Conf., June 1991, p. 164-169
4. H. Cho, G.D. Hachtel, F. Somenzi. Redundancy identification and removal based on implicit state enumeration. Proc. Intl. Conf. in Computer Design (ICCD-91), October 1991, p. 77-80
5. L. Entrena, K.-T. Cheng. Combinational and sequential logic optimization by redundancy addition and removal. IEEE Trans. on CAD, Vol. 14, No. 7, July 1995, p. 909-916
6. W. Kunz, D.K. Pradhan. Recursive learning: an attractive alternative to the decision tree test generation in digital circuits. Proc. Intl. Test Conf., October 1992, p.816-825
7. R. E. Bryant. Symbolic Boolean Manipulation with Ordered Binary Decision Diagrams. ACM Computing Surveys, Vol. 24, Nr. 3, 1992, p. 293-318
8. C. Chang, K.-T. Cheng, N.-S. Woo, M. Marek-Sadowska. Layout Driven Logic Synthesis for FPGAs. Proc. DAC-94, p. 308-313. June, 1994
9. S. C. Chang, M. Marek-Sadowska. Perturb and Simplify: Multi-level Boolean Network Optimizer. Proc. ICCAD-94, p. 2-5. November, 1994
10. W. Kunz, P. R. Menon. Multi-level Logic Optimization by Implication Analysis. Proc. ICCAD-94, p. 6-13. November, 1994
11. U. Gläser, K.-T. Cheng. Logic Optimization by an Improved Sequential Redundancy Addition and Removal Technique. Proc. ASP-DAC. September, 1995
12. L. Entrena, J. A. Espejo, E. Olías, J. Uceda. Timing Optimization by an Improved Redundancy Addition and Removal Technique. Proc. EURODAC'96, p. 342-347. September 1996
13. T. Kirkland, M. R. Mercer. A Topological Search Algorithm for ATPG. Proc. ACM/IEEE 24th Design Automation Conf., p. 502-508. June, 1987
14. J.R. Burch, E.M. Clarke, K.L. McMillan, D.L. Dill, L.J. Hwang. Symbolic Model Checking: 1020 States and Beyond. LICS'90: 5th Annual IEEE Symposium on Logic in Computer Science, p. 428-439, June 1990