Resolving register bank conflicts for a network processor

Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT

Volumn 2003-January, Issue , 2003, Pages 269-278

  Zhuang, X ^a   Pande, Santosh ^a  

^a Georgia Institute of Technology   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMBINATORIAL OPTIMIZATION; NETWORK ARCHITECTURE; PARALLEL ARCHITECTURES;

ASSIGNMENT PROBLEMS; CONFLICT GRAPH; LOW QUALITIES; NETWORK PROCESSOR; PHASE ORDERING; REGISTER ALLOCATION; REGISTER BANK; REGISTER PRESSURE;

PARALLEL PROCESSING SYSTEMS;

EID: 84968752811     PISSN: 1089795X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/PACT.2003.1238022     Document Type: Conference Paper

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